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| CDP1853, CDP1853C March 1997 N-Bit 1 of 8 Decoder Description The CDP1853 and CDP1853C are 1 of 8 decoders designed for use in general purpose microprocessor systems. These devices, which are functionally identical, are specifically designed for use as gated N-bit decoders and interface directly with the 1800-series microprocessors without additional components. The CDP1853 has a recommended operating voltage range of 4V to 10.5V, and the CDP1853C has a recommended operating voltage range of 4V to 6.5V. When CHIP ENABLE (CE) is high, the selected output will be true (high) from the trailing edge of CLOCK A (high-to-low transition) to the trailing edge of CLOCK B (high-to-low transition). All outputs will be low when the device is not selected (CE = 0) and during conditions of CLOCK A and CLOCK B as shown in Figure 2. The CDP1853 inputs N0, N1, N2, CLOCK A, and CLOCK B are connected to an 1800-series microprocessor outputs N0, N1, N2, TPA, and TPB respectively, when used to decode I/O commands as shown in Figure 5. The CHIP ENABLE (CE) input provides the capability for multiple levels of decoding as shown in Figure 6. The CDP1853 can also be used as a general 1 of 8 decoder for I/O and memory system applications as shown in Figure 4. The CDP1853 and CDP1853C are supplied in hermetic 16-lead dual-in-line ceramic (D suffix) and plastic (E suffix) packages. Features * Provides Direct Control of Up to 7 Input and 7 Output Devices * CHIP ENABLE (CE) Allows Easy Expansion for Multilevel I/O Systems Ordering Information PACKAGE TEMP. RANGE PDIP Burn-In SBDIP Burn-In -40oC to +85oC 5V 10V PKG. NO. -40oC to +85oC CDP1853CE CDP1853CEX CDP1853E E16.3 E16.3 CDP1853CD CDP1853D D16.3 CDP1853CDX D16.3 Pinout 16 LEAD DIP TOP VIEW CLK A 1 N0 2 N1 3 OUT 0 4 OUT 1 5 OUT 2 6 OUT 3 7 VSS 8 16 VDD 15 CLK B 14 N2 13 CE 12 OUT 4 11 OUT 5 10 OUT 6 9 OUT 7 CDP1853 Functional Diagram CE 4 N0 2 5 6 N1 3 1 OF 8 DECODER 7 12 11 10 EN CE 13 9 OUT 0 OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 TRUTH TABLE CL A 0 0 1 1 X CL B 0 1 0 1 X EN Qn-1 1 0 1 0 1 1 1 1 0 N2 14 N2 0 N1 0 0 1 1 0 0 1 1 X N0 0 1 0 1 0 1 0 1 X EN 1 1 1 1 1 1 1 1 0 01234567 10000000 01000000 00100000 00010000 00001000 00000100 00000010 00000001 00000000 1 CLOCK A (TPA) Qn 0 0 0 15 CLOCK B (TPB) 1 1 1 1 FIGURE 1. X 1 = High level, 0 = Low level, X = Don't care Qn-1 = Enable remains in previous state. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 File Number 1189.2 4-35 CDP1853, CDP1853C Absolute Maximum Ratings DC Supply Voltage Range, (VDD) (All voltage values referenced to VSS terminal) CDP1853 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1853C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, any One Input . . . . . . . . . . . . . . . . . . . . . . . . .10mA Thermal Information Thermal Resistance (Typical) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 85 N/A SBDIP Package . . . . . . . . . . . . . . . . . . 85 22 Operating Temperature Range (TA) Ceramic Packages (D Suffix Types) . . . . . . . . . . -55oC to +125oC Plastic Packages (E Suffix Types) . . . . . . . . . . . . . -40oC to +85oC Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering). . . . . . . . . . . . . . . . . . +265oC At distance 1/16 1/32 In. (1.59 0.79mm) from case for 10s max CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Static Electrical Specifications At TA = -40 to +85oC, Unless Otherwise Specified CONDITIONS CDP1853 VO (V) VIN (V) 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 VDD (V) 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 (NOTE1) TYP 1 10 3.2 5.2 -2.3 -5.2 0 0 5 10 50 150 5 10 LIMITS CDP1853C (NOTE1) TYP 5 3.2 -2.3 0 5 50 5 10 PARAMETER Quiescent Device Current IL MIN 1.6 2.6 -1.15 -2.6 4.9 9.9 3.5 7 - MAX 10 100 0.1 0.1 1.5 3 1 1 100 300 7.5 15 MIN 1.6 -1.15 4.9 3.5 - MAX 50 0.1 1.5 1 100 7.5 15 UNITS A A mA mA mA mA V V V V V V V V A A A A pF pF - Output Low Drive (Sink) Current IOL 0.4 0.5 Output High Drive (Source) Current IOH 4.6 9.5 Output Voltage Low Level (Note 2) VOL - Output Voltage High Level VOH - Input Low Voltage VIL 0.5, 4.5 1, 9 Input High Voltage VIH 0.5, 4.5 1, 9 Input Leakage Current IIN Any Input Operating Current (Note 3) IDD1 0, 5 0, 10 0, 5 0, 10 - Input Capacitance Output Capacitance NOTES: CIN COUT - 1. Typical values are for TA = +25oC and nominal voltage. 2. IOL = IOH = 1A 3. Operating current measured in a CDP1802 system at 2MHz with outputs floating. Spec Number 4-36 CDP1853, CDP1853C Recommended Operating Conditions At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: LIMITS CDP1853 PARAMETER Supply Voltage Range Recommended Input Voltage Range MIN 4 VSS MAX 10.5 VDD MIN 4 VSS CDP1853C MAX 6.5 VDD UNITS V V Dynamic Electrical Specifications Unless Otherwise Specified At TA = -40 to +85oC, VDD = 5%, VIH = 0.7VDD, VIL = 0.3VDD, tR, tF = 20ns, CL = 100pF, LIMITS CDP1853 PARAMETER Propagation Delay Time: CE to Output tEOH, tEOL tNOH, tNOL tAO 5 10 5 10 5 10 Clock B to Output tBO 5 10 Minimum Pulse Widths: Clock A tCACA 5 10 Clock B tCBCB 5 10 NOTES: 1. Maximum limits of minimum characteristics are the values above which all devices function. 2. Typical values are for TA = +25oC and nominal voltages. 50 25 50 25 75 50 75 50 50 50 75 75 175 90 225 120 200 100 175 90 275 150 350 200 300 150 275 150 175 225 200 175 275 350 300 275 ns ns ns ns ns ns ns ns ns ns ns ns ns VDD (V) MIN TYP MAX MIN CDP1853C TYP MAX UNITS N to Output Clock A to Output 4-37 CDP1853, CDP1853C Timing Diagrams tEO CE OUTPUT tEO N OUTPUT tNO tNO FIGURE 2A. CE TO OUTPUT (0-7) DELAY TIME tCACA tAO FIGURE 2B. N LINES TO OUTPUT (0-7) DELAY TIME tCBCB tBO CLOCK B CLOCK A OUTPUT OUTPUT FIGURE 2C. CLOCK A TO OUTPUT (0-7) DELAY TIME FIGURE 2D. CLOCK B TO OUTPUT (0-7) DELAY TIME FIGURE 2. PROPAGATION DELAY TIME DIAGRAMS OUT 0 TPA TPB CE EN (NOTE 1) OUTPUT NOTE 1. OUTPUT ENABLED WHEN EN = HIGH INTERNAL SIGNAL SHOWN FOR REFERENCE ONLY (SEE FIGURE 1) A B C CHIP ENABLE VDD N0 N1 N2 CE CLOCK B CLOCK A OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 FIGURE 3. TIMING DIAGRAM FIGURE 4. N-BIT DECODER USED AS A 1 OF 8 DECODER 4-38 CDP1853, CDP1853C CDP1800 SERIES N0 N1 N2 VDD CLOCK A CLOCK B CE N0 N1 N2 CDP1853 01 2-6 7 READ VIA 6F INSTRUCTION LOAD VIA 67 INSTRUCTION DATA AVAILABLE CS1 CS2 CDP1852 OUTPUT DATA PORT 7 SR MODE TPB VDD 5 CDP1852 INPUT AND OUTPUT PORTS CS1 CS2 DATA STROBE CDP1852 INPUT PORT 7 MODE TPA TPB TPB MRD CLOCK READ VIA 69 INSTRUCTION LOAD VIA 61 INSTRUCTION AVAILABLE CS2 CS1 CDP1852 OUTPUT PORT 1 SR TPB MODE VDD 7 OUTPUT PORTS CS1 CS2 DATA STROBE CLOCK 7 INPUT PORTS CDP1852 INPUT PORT 1 MODE FIGURE 5. N-BIT DECODER IN A ONE-LEVEL I/O SYSTEM NO, N1, N2 CDP1800 SERIES TPA TPB MRD BUS NOTE: SYSTEM SHOWN WILL SELECT UP TO 56 INPUT AND 48 OUTPUT PORTS. WITH ADDITIONAL DECODING THE TOTAL NUMBER OF INPUT AND OUTPUT PORTS CAN BE DATA BUS FURTHER EXPANDED. TPA CDP1853 I DECODED "61" INSTRUCTION CL CSI CS2 CDP1852 INTERCONNECTED AS IN FIGURE 4 NO, N1, N2 CLOCK A CLOCK B CE CDP1853 "62-6F" INST CLOCK A CLOCK B CE CDP1853 "62-6F" INST SECTIONS 3-7 CLOCK A CLOCK B CE CDP1853 "62-6F" INST I/O 7 INPUT 6 OUTPUT PORTS NO, N1, N2 I/O 7 INPUT 6 OUTPUT PORTS NO, N1, N2 I/O 7 INPUT 6 OUTPUT PORTS FIGURE 6. TWO-LEVEL I/O USING CDP1853 AND CDP1852 4-39 CDP1853, CDP1853C All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 4-40 |
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